TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-09-14
TSMC reported record-breaking monthly revenue for August 2026, driven by insatiable AI demand that has forced the company to announce aggressive capacity expansion plans for its CoWoS advanced packaging and N2/N3 nodes through 2028. Supply chain constraints remain acute, with equipment demand doubling and orders spilling over to rivals like Intel and ASE as TSMC struggles to keep pace with hyperscaler requirements.
TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-09-14
Top developments
TSMC Plans to Double CoWoS Capacity by 2028
TSMC is preparing a major expansion of its advanced CoWoS packaging capacity, targeting a rise from approximately 130,000 wafer equivalents per month (WPM) by the end of 2026 to roughly 260,000 WPM by the end of 2028. This doubling of capacity is a direct response to AI chip demand that continues to outstrip supply, with the expansion focused on new facilities in Arizona (AP9, AP10) and Taiwan (AP7). The move acknowledges that even with current aggressive ramps, a supply-demand gap persists, prompting TSMC to look beyond its own internal capacity limits.
Record August Revenue Hits NT$514.8 Billion
TSMC announced its consolidated revenue for August 2026 reached NT$514.81 billion, marking a 53.3% year-over-year increase and a 10.1% month-over-month growth. This figure represents the first time monthly revenue has surpassed NT$500 billion, extending a streak of four consecutive months of record highs. The surge is primarily attributed to the robust demand for AI-related chips and high-performance computing applications, which continue to strain foundry capacity across advanced nodes.
Orders Spill Over to Rivals as Capacity Hits Limits
Despite TSMC’s rapid expansion, the shortage of CoWoS packaging capacity has led to a spillover effect, with customers increasingly turning to non-TSMC providers. Analysts note that Intel, ASE, Amkor, and silicon interposer suppliers like UMC and World Advanced are seeing accelerated demand growth as they capture the overflow from TSMC’s saturated lines. This shift highlights a structural bottleneck in the AI chip supply chain where packaging, rather than wafer fabrication, has become the critical constraint on shipment volumes.
N2 and N3 Ramps Accelerate for 2027 Targets
Supply chain sources indicate that TSMC has disclosed its latest expansion targets for its most advanced nodes, with N2 capacity expected to grow from 90,000 WPM at the end of 2026 to 110,000 WPM by mid-2027, a 22% increase. Simultaneously, N3 capacity is projected to rise from over 180,000 WPM to 210,000 WPM in the same period, an increase of more than 16%. These ramps are essential to meet the anticipated wave of next-generation AI accelerators and mobile processors scheduled for late 2027 and early 2028.
Local view
Taiwanese media outlets such as United Daily News (UDN) and Peoplenews are focusing heavily on the "spillover" phenomenon, noting that TSMC’s inability to fully satisfy domestic and international demand is creating opportunities for local OSATs (Outsourced Semiconductor Assembly and Test) and rival foundries. Peoplenews reports that TSMC is strategically outsourcing certain packaging steps to partners like ASE and Amkor to keep the overall AI chip production line flowing, rather than trying to handle every step internally. Meanwhile, Sammy Fans highlights TSMC’s promotion of a new "System Technology Collaborative Optimization" (STCO) framework, urging closer cooperation between chip designers, equipment makers, and material suppliers to alleviate bottlenecks.
Context & numbers
- CoWoS Capacity: Current estimates place TSMC’s CoWoS capacity at ~130,000 WPM by end-2026, with a target of ~260,000 WPM by end-2028.
- August Revenue: NT$514.81 billion (+53.3% YoY), breaking the NT$500 billion threshold for the first time.
- South Korea Export Data: Semiconductor exports from South Korea hit a record $34.97 billion in the first ten days of September 2026, accounting for 47% of total outbound shipments, reflecting the global AI chip boom’s impact on regional trade balances.
- Foundry Market Share: TSMC’s global wafer foundry market share reached 72.5% in Q2 2026, widening the gap with Samsung.
On the radar
- STCO Implementation: Watch for early adopters of TSMC’s System Technology Collaborative Optimization (STCO) initiative, which aims to streamline the entire AI chip development chain from design to packaging.
- Arizona Fab Yield Updates: Continued focus on whether Arizona’s Fab 21 can maintain parity with Taiwan yields as it scales up N3 and prepares for N2, a critical factor for US-based customers seeking supply chain diversification.
- Intel’s Bridge-Based Packaging: Intel is reportedly targeting 45,000 wafer-equivalents of bridge-based packaging capacity by 2028, specifically aiming to capture custom AI chip orders from Google and Amazon that TSMC cannot fulfill.
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