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TSMC CoWoS, Foundry Capacity and AI Chip Supply

TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-09-03

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TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-09-03

TSMC CoWoS, Foundry Capacity and AI Chip Supply|September 3, 2026(1h ago)3 min read9.3AI quality score — automatically evaluated based on accuracy, depth, and source quality
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TSMC executives confirmed at SEMICON Taiwan 2026 that equipment demand has nearly doubled in six months, driving 2026 CapEx toward $64 billion as the company races to expand CoWoS and N2 capacity. While market rumors suggested a slowdown in advanced packaging orders, TSMC clarified that the delay reflects a strategic shift toward next-generation CoPoS technology rather than weak AI demand. Meanwhile, MediaTek’s CEO publicly pleaded for more capacity from TSMC and ASE, highlighting persistent bottlenecks in the global AI chip supply chain.

TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-09-03


Top developments


Equipment demand doubles, CapEx hits $64B

TSMC Senior Vice President C.C. Wei revealed that the company's demand for fab equipment has increased from 1X (estimated last year) to 1.9X by July 2026, nearly doubling in six months due to surging AI workloads. This acceleration has pushed TSMC’s 2026 capital expenditure guidance toward the upper end of $64 billion, with significant allocations for new fabs and advanced packaging lines. The surge is stretching the global semiconductor supply chain beyond its usual planning cycles, causing labor shortages and infrastructure constraints not just in Taiwan but in the US and Japan.

TSMC executive discussing equipment demand
TSMC executive discussing equipment demand

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com


CoWoS order delay misinterpreted; focus shifts to CoPoS

Reports that TSMC delayed placing 2027 advanced packaging equipment orders sparked speculation of excess CoWoS capacity. However, equipment suppliers and industry analysts clarify that CoWoS demand remains robust; the delay is a strategic move to prepare for the mass production of Chip-on-Panel-on-Substrate (CoPoS). This next-generation packaging technology aims to overcome the physical size limits of current silicon interposers, allowing for larger AI chiplets and higher integration density.

CoWoS packaging diagram
CoWoS packaging diagram

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com

digitimes.com


MediaTek CEO pleads for capacity at SEMICON

During the SEMICON Taiwan 2026 Master Forum, MediaTek CEO Cai Xingli (Cliff Tsai) humorously but urgently requested more production capacity from TSMC and ASE for 2027–2029. The plea underscores the severe tightness in the foundry and OSAT sectors, where major customers like NVIDIA and Apple are likely prioritizing their own allocations. This public demand highlights the competitive pressure on TSMC to balance its own aggressive expansion with customer commitments.

MediaTek CEO at SEMICON Forum
MediaTek CEO at SEMICON Forum

udn.com

udn.com

pgw.udn.com.tw

pgw.udn.com.tw


3DIC Alliance targets mass production efficiency

At the 3DIC Global Summit held on September 1, TSMC and ASE executives emphasized that the industry is moving from capacity expansion to "mass production efficiency." The 3DIC Alliance, now in its second year, is focusing on standardizing processes to improve yields for complex heterogeneous integration. TSMC’s VP Jun He noted that while CoWoS yields are exceeding 98%, scaling to larger reticle sizes requires tighter control over thermal and mechanical stress.


Local view

Local Taiwanese media outlets such as Commercial Times and UDN are closely tracking the SEMICON Taiwan 2026 event, which opened on August 31. Reports highlight that over 100,000 professionals attended, with a strong focus on how AI chips' bottleneck has shifted from wafer production to the "wires" connecting them—specifically advanced packaging and interconnects. Local analysts note that while TSMC's Arizona fab is contributing significantly to group sales, the core innovation and high-volume manufacturing for leading-edge nodes remain concentrated in Taiwan, sustaining local supplier demand for equipment and materials.


Context & numbers

  • CapEx Guidance: TSMC’s 2026 capital expenditure is trending toward $64 billion, up from previous estimates, driven by equipment demand rising from 1X to 1.9X in six months.
  • CoWoS Capacity: Monthly CoWoS capacity is projected to reach 120,000–140,000 wafers by the end of 2026, narrowing the supply-demand gap from 20% to roughly 10%.
  • Arizona Performance: TSMC’s Arizona fab crossed 4% of group sales in Q2 2026, with revenue topping NT$40 billion, though profit margins remain under pressure compared to Taiwan operations.
  • Foundry Market Share: TSMC maintained a dominant 73% share of the global pure-play foundry market in Q2 2026, benefiting from a 29% YoY growth in the sector driven by AI.

On the radar

  • NVIDIA Earnings Impact: Investor sentiment remains volatile ahead of NVIDIA’s upcoming earnings, which will provide further clarity on AI chip demand sustainability and potential order adjustments for TSMC.
  • CoPoS Timeline: Watch for official announcements on the specific mass-production start date for CoPoS technology, which is expected to be a key differentiator in 2027.

This content was collected, curated, and summarized entirely by AI — including how and what to gather. It may contain inaccuracies. Crew does not guarantee the accuracy of any information presented here. Always verify facts on your own before acting on them. Crew assumes no legal liability for any consequences arising from reliance on this content.

Explore related topics
  • QWhat is CoPoS and how does it differ from CoWoS?
  • QHow are NVIDIA and Apple responding to capacity shortages?
  • QWill TSMC's $64B CapEx prevent future AI chip bottlenecks?

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