TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-10-25
TSMC's advanced packaging capacity remains the critical bottleneck for AI chip supply, with CoWoS demand outstripping production despite aggressive expansion. Meanwhile, the Japanese government has approved TSMC's Kumamoto Fab 2 for 3nm production, and Intel's CTO warned that EUV tool shortages will cap AI chip supply growth at roughly double current levels, far below demand.
TSMC CoWoS, Foundry Capacity and AI Chip Supply — 2026-10-25
Intel CTO Warns EUV Shortage Caps AI Supply Growth
Intel CTO Pushkar Ranade stated that ASML ships fewer than 70 extreme ultraviolet (EUV) lithography machines per year, a constraint that limits advanced wafer output to roughly double current levels. This cap is significantly below the tenfold growth implied by AI compute demand, regardless of foundry capacity expansion. This highlights that the AI chip supply chain is now constrained by upstream equipment availability as much as by foundry or packaging capacity.
Japan Approves TSMC Kumamoto Fab 2 for 3nm Production
Japan's Ministry of Economy, Trade and Industry (METI) officially approved TSMC's plan to upgrade its Kumamoto Fab 2 to produce 3nm chips, with production scheduled to begin in December 2028. This marks the first time 3nm chip production will occur within Japan, signaling a deepening of TSMC's global manufacturing footprint and a strategic shift toward advanced node localization in allied nations.
TSMC Arizona Fab Exceeds 100 Million Chips for Apple
TSMC's Arizona facility produced more than 100 million chips for Apple in 2026, spanning iPhone, iPad, and Apple Watch products. This milestone underscores the rapid ramp-up of TSMC's US operations, which are increasingly critical for reducing geopolitical risk and meeting US domestic demand for consumer electronics and potentially AI accelerators.
CoWoS Supply-Demand Gap Narrowing but Still Critical
While TSMC continues to accelerate advanced packaging capacity expansion, the supply-demand gap for CoWoS is reportedly narrowing from 20% to 10% by the end of 2026. Despite this improvement, major AI chip designers like NVIDIA and AMD are still competing fiercely for limited packaging slots, indicating that advanced packaging remains the primary chokepoint for AI hardware availability.
Local view
Taiwanese Media Focus on Packaging Spillover and Supplier Benefits
Local outlets such as SETN and Chinatimes report that the complexity of CoWoS packaging is driving significant benefits for Taiwanese semiconductor supply chain players. As TSMC's capacity remains fully loaded, "spillover" orders are flowing to secondary OSAT (Outsourced Semiconductor Assembly and Test) providers and specialized equipment makers. SETN noted that six major Taiwanese firms in wafer foundry, advanced testing, and ASIC design are clear beneficiaries of this trend, with equipment manufacturers seeing order visibility extending into 2028.
Capital Expenditure Drives Supply Chain Confidence
SETN also highlighted that TSMC's raised capital expenditure guidance of $60–64 billion for 2026 provides clear visibility for supply chain partners. The investment focuses on N2 and N3 ramps, as well as CoWoS and SoIC packaging, ensuring that local suppliers of facility systems, special gases, and ultra-pure water have sustained demand.
Context & numbers
Capacity and Demand Metrics
- CoWoS Capacity: TSMC's CoWoS capacity is projected to reach 120,000–140,000 wafers per month by the end of 2026, up from 13,000 wafers per month at the end of 2023.
- Long-term Goal: Capacity is expected to double again to 260,000 wafers per month by the end of 2028.
- HPC Revenue Share: High-Performance Computing (HPC) accounted for 68% of TSMC's revenue in Q3 2026, up from 58% in 2025, reflecting the dominance of AI-driven demand.
- Chip Prices: As of early 2026, the unit price for 3nm (N3/N3E) wafers was approximately $19,500, with lead times exceeding 50 weeks.
On the radar
India's $655M Bet on 3D AI Chip Packaging
Madhya Pradesh State is investing $655 million in India's first 3D heterogeneous integration facility, aiming to bypass the limitations of current OSAT plants in Gujarat. This move signals India's ambition to enter the high-end packaging market, which is currently dominated by TSMC and its partners.
CoPoS Production Timeline
TSMC is targeting 2028 for mass production of its next-generation CoWoS-System-on-Wafer (CoPoS) technology, which is expected to further alleviate packaging constraints for next-generation AI chips. Meanwhile, competitors like Samsung face delays in alternative glass substrate technologies.
This content was collected, curated, and summarized entirely by AI — including how and what to gather. It may contain inaccuracies. Crew does not guarantee the accuracy of any information presented here. Always verify facts on your own before acting on them. Crew assumes no legal liability for any consequences arising from reliance on this content.
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